Eshs

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Contents

Intersteller to Esh's Conversion Video

https://youtu.be/P1-Usce5N1w

Esh Test ROM

Written by Matt Ownby in late 2020, this replaces the H8 ROM on the Esh PCB and quickly runs through a bunch of tests to mostly determine whether the PCB is working correctly. Source code included.

http://www.rulecity.com/esh/esh_test_v2.zip

Hardware

Schematics

http://www.rulecity.com/esh/esh-schematic-22mar2021.pdf

Memory Map

Address Range Description
0x0000-0x1FFF ROM H8
0x2000-0x3FFF ROM F8
0x4000-053FFF ROM E8
0x6000-073FFF ROM D8
0x8000-0x9FFF ROM C8
0xA000-0xDFFF Not connected
0xE000-0xE7FF CPU RAM (B8)
0xF000-0xF7FF Video RAM (F3)

Z80 Port Map

Address Range Direction Description
0xF0 In Control panel input. Only lower 6 data bits are used. Active low.
Bit Description
0 COIN 1
1 COIN 2
2 START 1
3 START 2
4 TEST
0xF1 In Control panel input. Only lower 6 data bits are used. Active low.
Bit Description
0 UP
1 DOWN
2 LEFT
3 RIGHT
4 ACTION 1
5 ACTION 2
0xF2 In Control panel input. Only lower 6 data bits are used.
0xF3 In Control panel input. Only lower 6 data bits are used.
0xF4 In/Out LD-V1000 data. Writing queues a command to be sent on the next command strobe. Reading reads the most recent byte received during last the status strobe.
0xF5 Out Misc value.
Bit Description
0 Not connected
1 is audio (1 = audio signal comes from a vertical counter (VA3), 0 = audio signal is low).
2,3 Bit 2 and 3 deal with whether to show the laserdisc image or not. If bit 3 is high, A7 of the RGB prom is also high, laserdisc video is suppressed, and bit 2 is ignored. If bit 2 is high (and bit 3 is low) A7 of the RGB prom is low, and laserdisc video is suppressed.
4-7 Bits 4-7 indirectly map to A8 of the RGB PROM. They are selectable via bits 6 and 7 of the tile attribute (video memory 0xF400-0xF7FF). Although the hardware applies no further restrictions on use, the Esh program will constantly cycle each of these bits. Bit 4 doesn't cycle at all and is always high. Bit 5 cycles at about 15 Hz. Bit 6 cycles at about 7.5 Hz. Bit 7 cycles at about 4.3 Hz. The game uses this for variable blink speed.
0xF8 Out 0 disables start 1 button lamp. 1 enables.
0xF9 Out Start 2 button lamp. 0 disables, 1 enables.
0xFA Out 0 disables action button lamp. 1 enables.
0xFB Out 0 disables joystick lamp. 1 enables.
0xFC Out Not connected
0xFD Out Not connected
0xFE Out 0 holds IRQ' line high (disabled) by forcing a latch to be clear. 1 stops forcing latch to be clear, which allows IRQs to set the latch.
0xFF Out 0 holds NMI' line high (disabled) by forcing a latch to be clear. 1 stops forcing latch to be clear, which allows NMIs to set the latch.

Z80 Interrupts

NMI: Caused by LD-V1000 status strobe going low (becoming active)

IRQ: Caused by D2 output (pin 10) on vertical PROM (C6) transitioning from 0 to 1. This ends up being 60 Hz (vsync).

Video RAM Structure

Screen is divided into 32x32 tiles. The first tile is the top left.

0xF000-0xF3FF contain which tile to show.

0xF400-0xF7FF contain tile attributes. For example, 0xF400 would have attributes about the tile index at 0xF000.

Bit Description
0-3 Which color palette to use for the tile.
5-6 Not used
6-7 Blink frequency. 0: no blinking, 1: blink at about 15 Hz, 2: blink at about 7.5 Hz, 3: blink at about 4.3 Hz ; The blink frequency is controlled by the Z80 program, and is not a hardware restriction.

PROM replacements

H and V PROMs are MB7052. I've replaced them with a single CPLD chip, the Xilinx XC9536XL-5VQG44C.

RGB PROM is MB7124. MB7124 are compatible with 82s147 proms which I have found to work. If these become unavailable, the CPLD option is my recommendation. I would also use the SN74LVC4245A in order to output 5V.

Audio

Sampled from pin 1 of the audio connector on the Esh PCB (CN1).

Esh audio buzz.png

Lamps

D2 on the Esh PCB will connect lamp lines to ground when the lamp is to be enabled. Therefore, if testing with, for example, a 20mA LED and 12V power, you would need to to wire one end of the LED to 12V and a 820 ohm resistor, and the other end to the output of one of the D2 lines. Once a path to ground is created, the LED will light up.

  1. LAMP_JOYSTICK will light up when a valid joystick move needs to be made in order to not die.
  2. LAMP_ACTION will light up when a valid action button move needs to be made in order to not die.
  3. LAMP_START1 and LAMP_START2 light up when the associated buttons may be pressed to start a game.


Troubleshooting

Timing Troubleshooting

Unplug edge connector and apply only 5V/GND to PCB edge. Unplugging edge connector removes ambiguity about whether timing is coming from laserdisc player sync or PCB-generated sync (which is slightly different).

Esh minimal power.jpg

Check B7, pin 3. Must be stable 18.432 MHz clock. If not stable, check resistors/cap near clock.

Esh B7 P3.png

Check B7, pin 10. Must be stable 6.144 MHz clock. If not stable, check B3 and A5.

Esh B7 P10.png

With sync PROMS removed, check B7 pin 14. Must be stable 12 kHz clock. (this is the 6.144MHz clock divided by 512)

Esh B6 P14 no sync prom.png

With sync PROMS installed, check B7, pin 14. Must be stable 15.63 kHz clock. If not stable, check H PROM (C5) and all of the horizontal counters (B6, B5, B4, and B3).

Esh B6 P14.png

Check D7, pin 12. Must be stable 59.5 Hz clock. If not, check vertical counters (C7, D7) and V PROM (C6). Strongly consider adding heat sink to V PROM.

Esh D7 P12.png

Check H7, pin 9 (CPU clock source). Must be stable 3.07 MHz clock.

If all is working, you can install the normal edge connector again.

"No Video" Troubleshooting

  1. Install Matt's Esh Test ROM into H8.
  2. Remove F8 ROM and B8 RAM to help isolate the problem.
  3. Attach logic analyzer to Z80 and power on PCB. Take logic analyzer capture of CPU's address/data lines after CPU has been on for a second or so. Make sure that CPU is looping in the "BAD RAM" part of the test ROM code (currently 0x9D5 - 0xA04 but this could change in the future). If it isn't, check K7 to make sure that basic routing is working.
  4. Check pin 21 (write) of F3, the video RAM, to make sure it is pulsing low.
  5. Check pin 11 of H1 (load) to make sure it is going high and low. Check pin 12 to make sure it is high.

Gameplay Troubleshooting

Having problems getting past Stage 4 after the giant sand fish emerges? Are you playing without the superimpose board? Make sure the edge connector pin 19 (DISC_VSYNC') is connected and edge connector pin V (DISC_CSYNC') is connected. Otherwise, you will not be able to play beyond this point. If you don't have a superimpose board, you can attach to Dexter's vsync and csync signals as a temporary workaround.

Dexter 3g vsync csync.png

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