Eshs
From DaphneWiki
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|Misc value? | |Misc value? | ||
|- | |- | ||
+ | |0xFE | ||
+ | |Out | ||
+ | |0 clears IRQ latch. 1 allows IRQs to be triggered. | ||
+ | |- | ||
+ | |0xFF | ||
+ | |Out | ||
+ | |0 clears NMI latch. 1 allows NMIs to be triggered. | ||
+ | |- | ||
+ | |||
|} | |} | ||
Revision as of 20:38, 13 August 2020
Contents |
Esh's Aurunmilla
Memory Map
Address Range | Description |
0x0000-0x1FFF | ROM H8 |
0x2000-0x3FFF | ROM F8 |
0x4000-053FFF | ROM E8 |
0x6000-073FFF | ROM D8 |
0x8000-0x9FFF | ROM C8 |
0xE000-0xE7FF | CPU RAM |
0xF000-0xF7FF | Unknown (Daphne says that this is video hardware) |
Z80 Port Map
Address Range | Direction | Description |
0xF0 | In | Control panel input. Only lower 6 data bits are used. |
0xF1 | In | Control panel input. Only lower 6 data bits are used. |
0xF2 | In | Control panel input. Only lower 6 data bits are used. |
0xF3 | In | Control panel input. Only lower 6 data bits are used. |
0xF4 | In/Out | LD-V1000 data. Writing queues a command to be sent on the next command strobe. Reading reads the most recent byte received during last the status strobe. |
0xF5 | Out | Misc value? |
0xFE | Out | 0 clears IRQ latch. 1 allows IRQs to be triggered. |
0xFF | Out | 0 clears NMI latch. 1 allows NMIs to be triggered. |
Interrupts
NMI: Caused by LD-V1000 status strobe going low (becoming active)
IRQ: Caused by D2 output (pin 10) on vertical PROM (C6) transitioning from 0 to 1.