Eshs
From DaphneWiki
(Difference between revisions)
(→Esh's Aurunmilla) |
(→Memory Map) |
||
(14 intermediate revisions not shown) | |||
Line 20: | Line 20: | ||
|0x8000-0x9FFF | |0x8000-0x9FFF | ||
|ROM C8 | |ROM C8 | ||
+ | |- | ||
+ | |0xA000-0xDFFF | ||
+ | |Not connected | ||
|- | |- | ||
|0xE000-0xE7FF | |0xE000-0xE7FF | ||
- | |CPU RAM | + | |CPU RAM (B8) |
|- | |- | ||
|0xF000-0xF7FF | |0xF000-0xF7FF | ||
- | | | + | |Video RAM (F3) |
|} | |} | ||
Line 36: | Line 39: | ||
|0xF0 | |0xF0 | ||
|In | |In | ||
- | |Control panel input. Only lower 6 data bits are used. | + | |Control panel input. Only lower 6 data bits are used. Active low. |
+ | |||
+ | {| border="1" cellpadding="2" cellspacing="0" | ||
+ | |'''Bit''' | ||
+ | |'''Description''' | ||
+ | |- | ||
+ | |0 | ||
+ | |COIN 1 | ||
+ | |- | ||
+ | |1 | ||
+ | |COIN 2 | ||
+ | |- | ||
+ | |2 | ||
+ | |START 1 | ||
+ | |- | ||
+ | |3 | ||
+ | |? (start 2? unconfirmed) | ||
+ | |- | ||
+ | |4 | ||
+ | |TEST | ||
+ | |- | ||
+ | |} | ||
+ | |||
|- | |- | ||
|0xF1 | |0xF1 | ||
|In | |In | ||
- | |Control panel input. Only lower 6 data bits are used. | + | |Control panel input. Only lower 6 data bits are used. Active low. |
+ | |||
+ | {| border="1" cellpadding="2" cellspacing="0" | ||
+ | |'''Bit''' | ||
+ | |'''Description''' | ||
+ | |- | ||
+ | |0 | ||
+ | |UP | ||
+ | |- | ||
+ | |1 | ||
+ | |DOWN | ||
+ | |- | ||
+ | |2 | ||
+ | |LEFT | ||
+ | |- | ||
+ | |3 | ||
+ | |RIGHT | ||
+ | |- | ||
+ | |4 | ||
+ | |ACTION BUTTON | ||
+ | |- | ||
+ | |} | ||
+ | |||
|- | |- | ||
|0xF2 | |0xF2 | ||
Line 56: | Line 103: | ||
|0xF5 | |0xF5 | ||
|Out | |Out | ||
- | |Misc value | + | |Misc value. |
+ | {| border="1" cellpadding="2" cellspacing="0" | ||
+ | |'''Bit''' | ||
+ | |'''Description''' | ||
|- | |- | ||
+ | |0 | ||
+ | |Not connected | ||
+ | |- | ||
+ | |1 | ||
+ | |is audio (1 = audio signal comes from a vertical counter (VA3), 0 = audio signal is low). | ||
+ | |- | ||
+ | |2,3 | ||
+ | |Bit 2 and 3 deal with whether to show the laserdisc image or not. If bit 3 is high, A7 of the RGB prom is also high, laserdisc video is suppressed, and bit 2 is ignored. If bit 2 is high (and bit 3 is low) A7 of the RGB prom is low, and laserdisc video is suppressed. | ||
+ | |- | ||
+ | |4-7 | ||
+ | |Bits 4-7 appear to decide whether A8 of the RGB prom is high/low depending on current position. This may be a way to have different pixels of a tile use a different color palette. | ||
|} | |} | ||
+ | |- | ||
+ | |0xF8 | ||
+ | |Out | ||
+ | |0 disables start button lamp. 1 enables. | ||
+ | |- | ||
+ | |0xF9 | ||
+ | |Out | ||
+ | |Drives EDGE_06 (on the edge connector), but we don't know what this is connected to. | ||
+ | |- | ||
+ | |0xFA | ||
+ | |Out | ||
+ | |0 disables action button lamp. 1 enables. | ||
+ | |- | ||
+ | |0xFB | ||
+ | |Out | ||
+ | |0 disables joystick lamp. 1 enables. | ||
+ | |- | ||
+ | |0xFC | ||
+ | |Out | ||
+ | |Not connected | ||
+ | |- | ||
+ | |0xFD | ||
+ | |Out | ||
+ | |Not connected | ||
+ | |- | ||
+ | |0xFE | ||
+ | |Out | ||
+ | |0 holds IRQ' line high (disabled) by forcing a latch to be clear. 1 stops forcing latch to be clear, which allows IRQs to set the latch. | ||
+ | |- | ||
+ | |0xFF | ||
+ | |Out | ||
+ | |0 holds NMI' line high (disabled) by forcing a latch to be clear. 1 stops forcing latch to be clear, which allows NMIs to set the latch. | ||
+ | |- | ||
+ | |||
+ | |} | ||
+ | |||
+ | === Z80 Interrupts === | ||
+ | NMI: Caused by LD-V1000 status strobe going low (becoming active) | ||
+ | |||
+ | IRQ: Caused by D2 output (pin 10) on vertical PROM (C6) transitioning from 0 to 1. This ends up being 60 Hz (vsync). | ||
+ | |||
+ | === Video RAM Structure === | ||
+ | |||
+ | Screen is divided into 32x32 tiles. The first tile is the top left. | ||
+ | |||
+ | 0xF000-0xF3FF contain which tile to show. | ||
+ | |||
+ | 0xF400-0xF7FF contain tile attributes. For example, 0xF400 would have attributes about the tile index at 0xF000. | ||
+ | |||
+ | === PROM replacements === | ||
+ | |||
+ | H and V PROMs are MB7052. MB7052 are compatible with 82s129 proms. One option is http://callanbrown.com/index.php/flep-prom-replacement-adapters | ||
+ | |||
+ | RGB PROM is MB7124. MB7124 are compatible with 82s147 proms. Haven't found replacement yet. | ||
+ | |||
+ | Newer EEPROMs may be fast enough. W27C512 may be a commonly available EEPROM. |
Revision as of 17:19, 16 September 2020
Contents |
Esh's Aurunmilla
Memory Map
Address Range | Description |
0x0000-0x1FFF | ROM H8 |
0x2000-0x3FFF | ROM F8 |
0x4000-053FFF | ROM E8 |
0x6000-073FFF | ROM D8 |
0x8000-0x9FFF | ROM C8 |
0xA000-0xDFFF | Not connected |
0xE000-0xE7FF | CPU RAM (B8) |
0xF000-0xF7FF | Video RAM (F3) |
Z80 Port Map
Address Range | Direction | Description | ||||||||||||
0xF0 | In | Control panel input. Only lower 6 data bits are used. Active low.
| ||||||||||||
0xF1 | In | Control panel input. Only lower 6 data bits are used. Active low.
| ||||||||||||
0xF2 | In | Control panel input. Only lower 6 data bits are used. | ||||||||||||
0xF3 | In | Control panel input. Only lower 6 data bits are used. | ||||||||||||
0xF4 | In/Out | LD-V1000 data. Writing queues a command to be sent on the next command strobe. Reading reads the most recent byte received during last the status strobe. | ||||||||||||
0xF5 | Out | Misc value.
| ||||||||||||
0xF8 | Out | 0 disables start button lamp. 1 enables. | ||||||||||||
0xF9 | Out | Drives EDGE_06 (on the edge connector), but we don't know what this is connected to. | ||||||||||||
0xFA | Out | 0 disables action button lamp. 1 enables. | ||||||||||||
0xFB | Out | 0 disables joystick lamp. 1 enables. | ||||||||||||
0xFC | Out | Not connected | ||||||||||||
0xFD | Out | Not connected | ||||||||||||
0xFE | Out | 0 holds IRQ' line high (disabled) by forcing a latch to be clear. 1 stops forcing latch to be clear, which allows IRQs to set the latch. | ||||||||||||
0xFF | Out | 0 holds NMI' line high (disabled) by forcing a latch to be clear. 1 stops forcing latch to be clear, which allows NMIs to set the latch. |
Z80 Interrupts
NMI: Caused by LD-V1000 status strobe going low (becoming active)
IRQ: Caused by D2 output (pin 10) on vertical PROM (C6) transitioning from 0 to 1. This ends up being 60 Hz (vsync).
Video RAM Structure
Screen is divided into 32x32 tiles. The first tile is the top left.
0xF000-0xF3FF contain which tile to show.
0xF400-0xF7FF contain tile attributes. For example, 0xF400 would have attributes about the tile index at 0xF000.
PROM replacements
H and V PROMs are MB7052. MB7052 are compatible with 82s129 proms. One option is http://callanbrown.com/index.php/flep-prom-replacement-adapters
RGB PROM is MB7124. MB7124 are compatible with 82s147 proms. Haven't found replacement yet.
Newer EEPROMs may be fast enough. W27C512 may be a commonly available EEPROM.